1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Background Art
FIG. 25 is a flowchart illustrating a method of manufacturing a conventional semiconductor device. FIGS. 26 to 29 are schematic diagrams illustrating steps in the process of manufacturing the conventional semiconductor device 300, FIGS. 26A, 27A, 28A, and 29A being top views, and FIGS. 26B, 27B, 28B, and 29B being sectional views.
A method of manufacturing a conventional semiconductor device 300 will be described below referring to FIGS. 25 to 29.
First, as shown in FIG. 26, ohmic electrodes 74 are formed on a semiconductor substrate 72 (Step S102). Here, a lift-off method is used. Considering the ease of lifting off, the ohmic electrodes 74 are formed in a combination of a C-shape and a reversed C-shape. Also considering the accuracy of mask alignment with electrodes and via holes formed later, the entire width of the ohmic electrodes 74 is controlled to W′.
Next, as FIG. 27 shows, an insulating film 76 is formed on the ohmic electrodes 74 and an exposed surface of the semiconductor substrate 72 (Step S104). Thereafter, contact holes 78 are formed in center portions of the ohmic electrodes 74 (Step S106). Wiring electrodes 80 are formed on the insulating film 76 using the lift-off method or the like so as to bury the contact holes 78 (Step S108). The wiring electrodes 80 have a barrier metal structure.
Next, as shown in FIG. 28, an insulating film 82 is formed on the wiring electrodes 80 and the exposed surface of the insulating film 76 (Step S110). From the insulating film 82, contact holes that open to the wiring electrodes 80 and a contact hole that opens to the portion to form a via hole are formed (Step S112). Thereafter a via hole 86 is formed from the contact hole for the via hole to the semiconductor substrate 72 (Step S114).
Next, a via-hole foundation electrode 88 is formed inside the via hole 86, on the insulating film 82, and on the exposed portion of the wiring electrodes 80 (Step S116). Then, a via-hole electrode 90 is formed on the surface of the via-hole foundation electrode 88 by using electroplating or the like (Step S120).
Next, as shown in FIG. 29, a back via hole 92 is formed (Step S122). The back via hole 92 is opened at a place corresponding to the via hole 86 opened from the surface. Thereafter, a back via-hole electrode 94 is formed on the exposed back surface of the semiconductor substrate 72 including the inside of the back via hole 92 using electroplating or the like (Step S124).
The conventional semiconductor device 300 is formed as described above (see Japanese Patent Laid-Open No. 10-64923, for example).
However, when a semiconductor device 300 is formed by using the method as described above, wiring electrodes 80 having a barrier metal structure must be inserted between the ohmic electrodes 74 and the via-hole electrode 90. For this reason, an additional margin for mask alignment is required. Therefore, there has been a problem that the width of the ohmic electrodes 74 must be increased for this margin resulting in increase in the lateral size of a semiconductor device.
Since a margin for mask alignment is also required between the ohmic electrodes 74 and the via hole 86 opened from the surface, this is also considered to increase the lateral size of a semiconductor device.